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mosel vitelic 1 v827332k04satg 2.5 volt 32m x 72 high performance unbuffered ecc ddr sdram module preliminary v827332k04satg rev. 1.1 july 2001 features 184 pin unbuffered 33,554,432 x 72 bit organization ddr sdram modules utilizes high performance 16m x 8 sdram in tsopii-66 packages single +2.5v (?0.2v) power supply programmable cas latency, burst length, and wrap sequence (sequential & interleave) auto refresh (cbr) and self refresh all inputs, outputs are sstl-2 compatible 4096 refresh cycles every 64 ms serial present detect (spd) ddr sdram performance description the v827332k04satg memory module is organized 33,554,432 x 72 bits in a 184 pin memory module. the 32m x 72 memory module uses 18 mosel-vitelic 16m x 8 ddr sdram. the x72 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. component used -7 -75 -8 units t ck clock frequency (max.) 143 (pc266a) 133 (pc266b) 125 (pc200) mhz t ac clock access time cas latency = 2.5 7758ns module speed a0 pc1600 (100mhz @ cl2) b0 pc2100b (133mhz @ cl2.5) b1 pc2100a (133mhz @ cl2)
2 mosel vitelic v827332k04satg v827332k04satg rev. 1.1 july 2001 part number information ddr 2.5v 8 mosel-vitelic manufactured v 184 pin unbuffered dimm x 8 component k refresh rate 4k 0 2 depth 32 4 banks 4 tsop width 73 sstl-2 s gold g t component rev a
mosel vitelic v827332k04satg 3 v827332k04satg rev. 1.1 july 2001 block diagram dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 7 i/o 6 i/o 1 i/o 0 d0 dm0 dm d8 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm i/o 7 i/o 6 i/o 1 i/o 0 d1 dm d9 i/o 5 i/o 4 i/o 3 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 dm1 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm i/o 7 i/o 6 i/o 1 i/o 0 d2 dm d10 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm2 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 7 i/o 6 i/o 1 i/o 0 d3 dm d11 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm3 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm i/o 7 i/o 6 i/o 1 i/o 0 d4 dm4 dm d12 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm i/o 7 i/o 6 i/o 1 i/o 0 d5 dm d13 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm5 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm i/o 7 i/o 6 i/o 1 i/o 0 d6 dm d14 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm i/o 7 i/o 6 i/o 1 i/o 0 d7 dm d15 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm7 a0 - a13 a0-a13: sdrams d0 - d15 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda ras ras : sdrams d0 - d15 cas cas : sdrams d0 - d15 cke0 cke: sdrams d0 - d7 we we : sdrams d0 - d15 cs0 cs1 cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs clock wiring ck0/ck0 clock input sdrams ck1/ck1 4 sdrams 6 sdrams 6 sdrams cke1 cke: sdrams d8 - d15 ba0 - ba1 ba0-ba1: sdrams d0 - d15 dqs0 dqs dqs4 dqs1 dqs5 dqs dqs dqs2 dqs dqs dqs3 dqs dqs dm6 dqs6 dqs7 dq15 i/o 2 i/o 5 dqs dqs dqs dqs dqs dqs dqs dqs dqs ck2/ck2 notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm resistors: 22 ohms. 4. vddid strap connections (for memory device vdd, vddq): strap out (open): vdd = vddq strap in (vss): vdd vddq. cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dm i/o 7 i/o 6 i/o 1 i/o 0 d8 dm d17 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm8 cs cs dqs8 dqs dqs *clock net wiring card edge dram1 dram2 dram4 dram5 dram6 r=120 ? dram3 *(cap.) *(cap.) cap will replace dram3,4 *if four drams are loaded, v ss d0 - d15 d0 - d15 v dd /v ddq d0 - d15 d0 - d15 vref v ddid strap: see note 4 0.1uf 0.1uf 0.1uf
4 mosel vitelic v827332k04satg v827332k04satg rev. 1.1 july 2001 pin configurations (front side/back side) notes: * these pins are not used in this module. pin front pin front pin front pin back pin back pin back 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 vref dq0 vss dq1 dqs0 dq2 vdd dq3 nc nc vss dq8 dq9 dqs1 vddq ck1 ck1 vss dq10 dq11 cke0 vddq dq16 dq17 dqs2 vss a9 dq18 a7 vddq dq19 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 a5 dq24 vss dq25 dqs3 a4 vdd dq26 dq27 a2 vss a1 cb0* cb1* vdd dqs8* a0 cb2* vss cb3* ba1 key dq32 vddq dq33 dqs4 dq34 vss ba0 dq35 dq40 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 vddq we dq41 cas vss dqs5 dq42 dq43 vdd nc dq48 dq49 vss ck2 ck2 vddq dqs6 dq50 dq51 vss vddid dq56 dq57 vdd dqs7 dq58 dq59 vss nc sda scl 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 vss dq4 dq5 vddq dm0 dq6 dq7 vss nc nc a13* vddq dq12 dq13 dm1 vdd dq14 dq15 cke1 vddq ba2* dq20 a12* vss dq21 a11 dm2 vdd dq22 a8 dq23 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 vss a6 dq28 dq29 vddq dm3 a3 dq30 vss dq31 cb4* cb5* vddq ck0* ck0 * vss dm8* a10 cb6* vddq cb7* key vss dq36 dq37 vdd dm4 dq38 dq39 vss dq44 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 ras dq45 vddq cs0 cs1 dm5 vss dq46 dq47 nc vddq dq52 dq53 nc vdd dm6 dq54 dq55 vddq nc dq60 dq61 vss dm7 dq62 dq63 vddq sa0 sa1 sa2 vddspd pin names pin pin description ck1, ck1 , ck2, ck2 differential clock inputs cs0 chip select input cke0 clock enable input ras , cas , we commend sets inputs a0 ~ a11 address ba0, ba1 bank address dq0~dq63 data inputs/outputs dqs0~dqs7 data strobe inputs/outputs dm0~dm7 data-in mask vdd power supply key key vddq dqs power supply vss ground vref reference power supply vddspd power supply for spd sa0~sa2 e 2 prom address inputs scl e 2 prom clock sda e 2 prom data i/o vddid vdd identification flag du do not use nc no connection pin pin description
mosel vitelic v827332k04satg 5 v827332k04satg rev. 1.1 july 2001 serial presence detect information bin sort: a0 (pc1600 @ cl2) b0 (pc2100b @ cl2.5) b1 (pc2100a @ cl2) byte # function described function supported hex value c b a c b a 0 defines # of bytes written into serial memory at module manufacturer 128bytes 80h 1 total # of bytes of spd memory device 256bytes 08h 2 fundamental memory type sdram ddr 07h 3 # of row address on this assembly 12 0ch 4 # of column address on this assembly 10 0ah 5 # of module rows on this assembly 2 bank 02h 6 data width of this assembly 72 bits 48h 7 .........data width of this assembly - 00h 8 vddq and interface standard of this assembly sstl 2.5v 04h 9 ddr sdram cycle time at cas latency =2.5 8ns 7.5ns 7ns 80h 75h 70h 10 ddr sdram access time from clock at cl=2.5 ?.8ns ?.75n ?.75n 80h 75h 75h 11 dimm configuration type(non-parity, parity, ecc) non-parity, ecc 00h 12 refresh rate & type 15.6us & self refresh 80h 13 primary ddr sdram width x8 08h 14 error checking ddr sdram data width x8 08h 15 minimum clock delay for back-to-back random column address t ccd =1clk 01h 16 ddr sdram device attributes : burst lengths supported 2,4,8 0eh 17 ddr sdram device attributes : # of banks on each ddr sdram 4 banks 04h 18 ddr sdram device attributes : cas latency supported 2,2.5 0ch 19 ddr sdram device attributes : cs latency 0clk 01h 20 ddr sdram device attributes : we latency 1clk 02h 21 ddr sdram module attributes registered address& control inputs and on-card dll 20h 22 ddr sdram device attributes : general +/-0.2v voltage tolerance 00h 23 ddr sdram cycle time at cl =2 10ns 10ns 7.5ns a0h a0h 75h 24 ddr sdram access time from clock at cl =2 ?.8ns ?.75n ?.75 80h 75h 75h 25 ddr sdram cycle time at cl =1.5 - - - 00h 26 ddr sdram access time from clock at cl =1.5 - - - 00h 27 minimum row precharge time (=t rp ) 20ns 20ns 20ns 50h 50h 50h 28 minimum row activate to row active delay(=t rrd ) 15ns 15ns 15ns 3ch 3ch 3ch
6 mosel vitelic v827332k04satg v827332k04satg rev. 1.1 july 2001 29 minimum ras to cas delay(=t rcd ) 20ns 20ns 20ns 50h 50h 50h 30 minimum active to precharge time(=t ras ) 48ns 48ns 45ns 30h 30h 2dh 31 module row density 128mb 20h 32 command and address signal input setup time 1.1ns 0.9ns 0.9ns b0h 90h 90h 33 command and address signal input hold time 1.1ns 0.9ns 0.9ns b0h 90h 90h 34 data signal input setup time 0.6ns 0.5ns 0.5ns 60h 50h 50h 35 data signal input hold time 0.6ns 0.5ns 0.5ns 60h 50h 50h 36-61 superset information (may be used in future) - 00h 62 spd data revision code initial release 00h 63 checksum for bytes 0 ~ 62 - 33h afh 7dh 64 manufacturer jedec id code mosel vitelic 40h 65 -71 ....... manufacturer jedec id code mosel vitelic 00h 72 manufacturing location 01h 73-90 module part number (ascii) v827332k04satg 91 manufacturer revison code (for pcb) 0 00 92 manufacturer revison code (for component) 0 00 93 manufacturing date (week) - - 94 manufacturing date (year) - - 95~98 assembly serial # - - 99~127 manufacturer specific data (may be used in future) undefined 00h 128~255 open for customer use undefined 00h byte # function described function supported hex value c b a c b a serial presence detect information (cont.)
mosel vitelic v827332k04satg 7 v827332k04satg rev. 1.1 july 2001 dc operating conditions (t a = 0 to 70?, voltage referenced to v ss = 0v) notes: 1. v ddq must not exceed the level of v dd . 2. v il (min) is acceptable -1.5v ac pulse width with 5ns of duration. 3. the value of v ref is approximately equal to 0.5v ddq . ac operating conditions (t a = 0 to 70 ?, voltage referenced to v ss = 0v) notes: 1. vid is the magnitude of the difference between the input level on ck and the input on ck. 2. the value of vix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. parameter symbol min typ. max unit note power supply voltage v dd 2.3 2.5 2.7 v power supply voltage v ddq 2.3 2.5 2.7 v 1 input high voltage v ih v ref + 0.15 - v ddq + 0.3 v input low voltage v il -0.3 - v ref - 0.15 v 2 i/o termination voltage v tt v ref - 0.04 v ref v ref + 0.04 v reference voltage v ref 1.15 1.25 1.35 v 3 input leakage current i i -2 - 2 ? output leakage current io z -5 - 5 ? output high current (v out = 1.95v) io h -16.8 - - ma output low current (v out = 0.35v) io l 16.8 - - ma parameter symbol min max unit note input high (logic 1) voltage, dq, dqs and dm signals v ih(ac) v ref + 0.31 v input low (logic 0) voltage, dq, dqs and dm signals v il(ac) v ref - 0.31 v input differential voltage, ck and ck inputs v id(ac) 0.7 v ddq + 0.6 v 1 input crossing point voltage, ck and ck inputs v ix(ac) 0.5*v ddq-0.2 0.5*v ddq+0.2 v2
8 mosel vitelic v827332k04satg v827332k04satg rev. 1.1 july 2001 ac operating test conditions (t a = 0 to 70?, voltage referenced to v ss = 0v) input/output capacitance (v dd = 2.5v, v ddq = 2.5v, t a = 25?, f = 1mhz) parameter value unit reference voltage v ddq x 0.5 v termination voltage v ddq x 0.5 v ac input high level voltage (v ih , min) v ref + 0.31 v ac input low level voltage (v il , max) v ref - 0.31 v input timing measurement reference level voltage v ref v output timing measurement reference level voltage v tt v input signal maximum peak swing 1.5 v input minimum signal slew rate 1 v/ns termination resistor (r t ) 50 ? series resistor (r s ) 25 ? output load capacitance for access time measurement (c l ) 30 pf parameter symbol min max unit input capacitance (a 0 ~ a 11 , ba 0 ~ ba 1 , ras , cas , we ) cin 1 60 75 pf input capacitance (cke 0 ) cin 2 40 48 pf input capacitance (cs 0 ) cin 3 40 48 pf input capacitance (clk 1 , clk 2 ) cin 4 30 32 pf data & dqs input/output capacitance (dq 0 ~dq 63 ) c out 10 12 pf input capacitance (dm0~dm8) cin 5 10 12 pf output load circuit (sstl_2) output z0=50 ? c load =30pf v ref =0.5*v ddq r t =50 ? v tt =0.5*v ddq
mosel vitelic v827332k04satg 9 v827332k04satg rev. 1.1 july 2001 ddr sdram i dd spec table * module i dd was calculated on the basis of component i dd and can be differently measured according to dq loading cap. detailed test conditions for ddr sdram idd1 & idd idd1 : operating current: one bank operation 1. typical case : vdd = 2.5v, t=25 c 2. worst case : vdd = 2.7v, t= 10 c 3. only one bank is accessed with trc(min), burst mode, address and control inputs on nop edge are changing once per clock cycle. lout = 0ma 4. timing patterns - ddr200(100mhz, cl=2) : tck = 10ns, cl2, bl=4, trcd = 2*tck, tras = 5*tck read : a0 n r0 n n p0 n a0 n - repeat the same timing with random address changing *50% of data changing at every burst - ddr266b(133mhz, cl=2.5) : tck = 7.5ns, cl=2.5, bl=4, trcd = 3*tck, trc = 9*tck, tras = 5*tck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing *50% of data changing at every burst - ddr266a (133mhz, cl=2) : tck = 7.5ns, cl=2, bl=4, trcd = 3*tck, trc = 9*tck, tras = 5*tck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing *50% of data changing at every burst legend : a=activate, r=read, w=write, p=precharge, n=nop symbol a0(pc1600@cl=2) b0(pc2100b@cl=2.5) b1(pc2100a@cl=2) unit typical worst typical worst typical worst idd0 1350 1440 1350 1440 1080 1170 ma idd1 1575 1710 1575 1710 1280 1395 ma idd2p 675 720 675 720 540 585 ma idd2f 655 945 655 945 720 765 ma idd2q 765 810 765 810 630 675 ma idd3p 720 765 720 765 585 630 ma idd3n 900 990 900 990 720 810 ma idd4r 1980 2250 1980 2250 1620 1845 ma idd4w 2115 2385 2115 2385 1710 1890 ma idd5 2115 2385 2115 2385 1710 1890 ma idd6 normal 36 36 36 36 36 36 ma low power 18 18 18 18 18 18 ma idd7 3375 3825 3375 3825 2745 3150 ma
10 mosel vitelic v827332k04satg v827332k04satg rev. 1.1 july 2001 ac characteristics (ac operating conditions unless otherwise noted) parameter symbol (pc1600) (pc2100b) (pc2100a) unit note min max min max min max row cycle time t rc 65 - 65 - 70 - ns auto refresh row cycle time t rfc 75 - 75 - 80 - ns row active time t ras 45 120k 48 120k 50 120k ns row address to column address delay t rcd 20 - 20 - 20 - ns row active to row active delay t rrd 15 - 15 - 15 - ns column address to column address delay t ccd 1 - 1 - 1 - clk row precharge time t rp 20 - 20 - 20 - ns write recovery time t wr 15 - 15 - 15 - ns last data-in to read command t drl 1 - 1 - 1 - clk auto precharge write recovery + precharge time t dal 35 - 35 - 35 - ns system clock cycle time cas latency = 2.5 t ck 7 15 7.5 15 8 15 ns cas latency = 2 7.5 15 10 15 10 15 ns clock high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 clk clock low level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 clk data-out edge to clock edge skew t ac -0.75 0.75 -0.75 0.75 -0.8 0.8 ns dqs-out edge to clock edge skew t dqsck -0.75 0.75 -0.75 0.75 -0.8 0.8 ns dqs-out edge to data-out edge skew t dqsq - 0.5 - 0.5 - 0.6 ns data-out hold time from dqs t qh t hpmin -0.75ns - t hpmin -0.75ns - t hpmin -0.75ns - ns 1 clock half period t hp t ch/l min - t ch/l min - t ch/l min - ns 1 input setup time (fast slew rate) t is 0.9 - 0.9 - 1.1 - ns 2,3,5,6 input hold time (fast slew rate) t ih 0.9 - 0.9 - 1.1 - ns 2,3,5,6 input setup time (slow slew rate) t is 1.0 - 1.0 - 1.1 - ns 2,4,5,6 input hold time (slow slew rate) t ih 1.0 - 1.0 - 1.1 - ns 2,4,5,6 input pulse width t ipw 2.2 - 2.2 - - - ns 6 write dqs high level width t dqsh 0.4 0.6 0.4 0.6 0.4 0.6 clk write dqs low level width t dqsl 0.4 0.6 0.4 0.6 0.4 0.6 clk clk to first rising edge of dqs-in t dqss 0.75 1.25 0.75 1.25 0.75 1.25 clk data-in setup time to dqs-in (dq & dm) t ds 0.5 - 0.5 - 0.6 - ns 7 data-in hold time to dqs-in (dq & dm) t dh 0.5 - 0.5 - 0.6 - ns 7 dq & dm input pulse width t dipw 1.75 - 1.75 - 2 - ns read dqs preamble time t rpre 0.9 1.1 0.9 1.1 0.9 1.1 clk read dqs postamble time t rpst 0.4 0.6 0.4 0.6 0.4 0.6 clk
mosel vitelic v827332k04satg 11 v827332k04satg rev. 1.1 july 2001 ac characteristics (cont.) notes: 1. this calculation accounts for tdqsq(max), the pulse width distortion of on-chip circuit and jitter. 2. data sampled at the rising edges of the clock : a0~a11, ba0~ba1, cke, cs , ras , cas , we . 3. for command/address input slew rate >=1.0v/ns 4. for command/address input slew rate >=0.5v/ns and <1.0v/ns 5. ck, ck slew rates are >=1.0v/ns 6. these parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester correlation. 7. data latched at both rising and falling edges of data strobes(dqs) : dq, dm 8. minimum of 200 cycles of stable input clocks after self refresh exit command, where cke is held high, is required to complet e self refresh exit and lock the internal dll circuit of ddr sdram. absolute maximum ratings note: operation at above absolute maximum rating can adversely affect device reliability write dqs preamble setup time t wpres 0 - 0 - 0 - clk write dqs preamble hold time t wpreh 0.25 - 0.25 - 0.25 - clk write dqs postamble time t wpst 0.4 0.6 0.4 0.6 0.4 0.6 clk mode register set delay t mrd 2 - 2 - 2 - clk power down exit time t pdex 10 - 10 - 10 - ns exit self refresh to non-read command t xsnr 75 - 75 - 80 - ns exit self refresh to read command t xsrd 200 - 200 - 200 - clk 8 average periodic refresh interval t refi - 15.6 - 15.6 - 15.6 us parameter symbol rating unit ambient temperature t a 0 ~ 70 c storage temperature t stg -55 ~ 125 c voltage on any pin relative to v ss v in , v out -0.5 ~ 3.6 v voltage on v dd relative to v ss v dd -0.5 ~ 3.6 v voltage on v ddq relative to v ss v ddq -0.5 ~ 3.6 v output short circuit current i os 50 ma power dissipation p d 8 w soldering temperature time t solder 260 10 c sec parameter symbol (pc1600) (pc2100b) (pc2100a) unit note min max min max min max
12 mosel vitelic v827332k04satg v827332k04satg rev. 1.1 july 2001 package dimensions 5.25 0.006 5.077 units : inches (millimeters) 0.050 0.0078 0.006 (0.20 0.15) 0.393 (10.00) (1.270) 0.100 (2.50 ) detail b a b 0.089 (2.26) (128.950) (133.350 0.15) 0.250 (6.350) detail a 0.157 (4.00) 0.071 (1.80) 0.039 0.002 (1.000 0.050) (3.80) 2.175 (6.62) (64.77) (49.53) (17.80) 2.55 1.95 0.26 0.7 0.1496 1.25 0.006 (31.75 0.15) (4.00) (2x) 0.157 0.142 max 0.050 0.0039 (1.270 0.10) (3.81 max)
mosel vitelic v827332k04satg 13 v827332k04satg rev. 1.1 july 2001 label information c l = 2.5 (clk) t rcd = 3 (clk) t rp = 3 (clk) 2533 unbuffered dimm pc2100u 08 spd revision 0 0 v827332k04satg-xx pc2100u-2533-080-a taiwan xxxx-xxxxxxx a gerber file jedec --- mosel vitelic part number dimm manufacture date code trace code a0: pc1600 (100mhz @ cl2) b0: pc2100b (133mhz @ cl2.5) b1: pc2100a (133mhz @ cl2)
mosel vitelic worldwide offices v827332k04satg ? copyright 2001, mosel vitelic inc. 7/01 printed in u.s.a. mosel vitelic 3910 n. first street, san jose, ca 95134-1501 ph: (408) 433-6000 fax: (408) 433-0952 tlx: 371-9461 the information in this document is subject to change without notice. mosel vitelic makes no commitment to update or keep cur- rent the information contained in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of mosel-vitelic. mosel vitelic subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica- tions. mosel vitelic does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil- ity for consequential or incidental arising from any use of its prod- ucts. if such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. u.s. sales offices u.s.a. 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 taiwan 7f, no. 102 min-chuan e. road, sec. 3 taipei phone: 886-2-2545-1213 fax: 886-2-2545-1209 no 19 li hsin road science based ind. park hsin chu, taiwan, r.o.c. phone: 886-3-579-5888 fax: 886-3-566-5888 singapore 10 anson road #23-13 international plaza singapore 079903 phone: 65-3231801 fax: 65-3237013 japan onze 1852 building 6f 2-14-6 shintomi, chuo-ku tokyo 104-0041 phone: 03-3537-1400 fax: 03-3537-1402 uk & ireland suite 50, grovewood business centre strathclyde business park bellshill, lanarkshire, scotland, ml4 3nq phone: 44-1698-748515 fax: 44-1698-748516 germany (continental europe & israel) benzstrasse 32 71083 herrenberg germany phone: +49 7032 2796-0 fax: +49 7032 2796 22 northwestern 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 southwestern 302 n. el camino real #200 san clemente, ca 92672 phone: 949-361-7873 fax: 949-361-7807 central, northeastern & southeastern 604 fieldwood circle richardson, tx 75081 phone: 214-826-6176 fax: 214-828-9754

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